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SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions Clock Sustained Execution Four 59 Mbytes s DMA Channels with Data Chaining Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture Two Instructions clock Execution Load Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulates 64-bit Bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model Fast Procedure Call Return Model Full Procedure Call in 4 Clocks On-Chip Register Cache Caches Registers on Call Ret Minimum of 6 Frames Provided Up to 15 Programmable Frames On-Chip instruction Cache 1 Kbyte Two-Way Set Associative 128-bit Path to instruction Sequencer Cache-Lock Modes Cache-Off Mode High Bandwidth On-Chip Data RAM 1 Kbyte On-Chip Data RAM Sustains 128 bits per Clock Access
Y
Four On-Chip DMA Channels 59 Mbytes s Fly-by Transfers 32 Mbytes s Two-Cycle Transfers Data Chaining Data Packing Unpacking Programmable Priority Method 32-Bit Demultiplexed Burst Bus 128-bit internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8- 16- or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin Selectable Big or Little Endian Byte Ordering High-Speed Interrupt Controller Up to 248 External interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four internal DMA Interrupts Separate Non-maskable interrupt Pin Context Switch in 750 ns Typical Product Grades Available SE3 b 40 C to a 110 C
Y
Y
Y
Y
Y
Y
Y
Y
December 1994
Order Number 271327-001
SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
CONTENTS
1 0 PURPOSE 2 0 80960CA OVERVIEW 2 1 The C-Series Core 2 2 Pipelined Burst Bus 2 3 Flexible DMA Controller 2 4 Priority Interrupt Controller 2 5 Instruction Set Summary 3 0 PACKAGE INFORMATION 3 1 Package Introduction 3 2 Pin Descriptions 3 3 80960CA Mechanical Data 3 3 1 80960CA PGA Pinout 3 4 Package Thermal Specifications 3 5 Stepping Register Information 3 6 Suggested Sources for 80960CA Accessories 4 0 ELECTRICAL SPECIFICATIONS 4 1 Absolute Maximum Ratings 4 2 Operating Conditions 4 3 Recommended Connections 4 4 DC Specifications 4 5 AC Specifications 4 5 1 AC Test Conditions 4 5 2 AC Timing Waveforms 4 5 3 Derating Curves 5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE 6 0 BUS WAVEFORMS 7 0 REVISION HISTORY PAGE
5 5 6 6 6 6 7 8 8 8 15 15 19 21 21 22 22 22 22 23 24 28 28 32 34 35 62
2
CONTENTS
LIST OF FIGURES Figure 1 80960CA Block Diagram Figure 2 80960CA PGA Pinout View from Top (Pins Facing Down) Figure 3 80960CA PGA Pinout View from Bottom (Pins Facing Up) Figure 4 Measuring 80960CA PGA Case Temperature Figure 5 Register g0 Figure 6 AC Test Load Figure 7 Input and Output Clocks Waveform Figure 8 CLKIN Waveform Figure 9 Output Delay and Float Waveform Figure 10 Input Setup and Hold Waveform Figure 11 NMI XINT7 0 Input Setup and Hold Waveform Figure 12 Hold Acknowledge Timings Figure 13 Bus Backoff (BOFF) Timings Figure 14 Relative Timings Waveforms Figure 15 Output Delay or Hold vs Load Capacitance Figure 16 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC Figure 17 ICC vs Frequency and Temperature Figure 18 Cold Reset Waveform Figure 19 Warm Reset Waveform Figure 20 Entering the ONCE State Figure 21 Clock Synchronization in the 2-x Clock Mode Figure 22 Clock Synchronization in the 1-x Clock Mode Figure 23 Non-Burst Non-Pipelined Requests without Wait States Figure 24 Non-Burst Non-Pipelined Read Request with Wait States Figure 25 Non-Burst Non-Pipelined Write Request with Wait States Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus
PAGE
5 17 18 19 21 28 28 28 29 29 30 30 31 32 32 33 33 35 36 37 38 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
3
CONTENTS
LIST OF FIGURES (Continued) Figure 38 Using External READY Figure 39 Terminating a Burst with BTERM Figure 40 BOFF Functional Timing Figure 41 HOLD Functional Timing Figure 42 DREQ and DACK Functional Timing Figure 43 EOP Functional Timing Figure 44 Terminal Count Functional Timing Figure 45 FAIL Functional Timing Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) Figure 48 Idle Bus Operation LIST OF TABLES Table 1 80960CA Instruction Set Table 2 Pin Description Nomenclature Table 3 80960CA Pin Description External Bus Signals Table 4 80960CA Pin Description Processor Control Signals Table 5 80960CA Pin Description DMA and Interrupt Unit Control Signals Table 6 80960CA PGA Pinout In Signal Order Table 7 80960CA PGA Pinout In Pin Order Table 8 Maximum TA at Various Airflows in C Table 9 80960CA PGA Package Thermal Characteristics Table 10 Die Stepping Cross Reference Table 11 Operating Conditions (80960CA-25 -16) Table 12 DC Characteristics Table 13 80960CA AC Characteristics (25 MHz) Table 14 80960CA AC Characteristics (16 MHz) Table 15 Reset Conditions Table 16 Hold Acknowledge and Backoff Conditions
PAGE
54 55 56 57 58 58 59 59 60 61 62
7 8 9 12 14 15 16 19 20 21 22 23 24 26 34 34
4
SPECIAL ENVIRONMENT 80960CA-25 -16
A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte s bandwidth to a system's highspeed external memory sub-system In addition the 80960CA's on-chip caching of instructions procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system's slower cost sensitive main memory subsystem The 80960CA bus controller integrates full wait state and bus width control for highest system performance with minimal system design complexity Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CA The processor also integrates four complete datachaining DMA channels and a high-speed interrupt controller on-chip DMA channels perform singlecycle or two-cycle transfers data packing and unpacking and data chaining Block transfers in addition to source or destination synchronized transfers are provided The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (``latency'') time of 750 ns
1 0 PURPOSE
This document provides electrical characteristics for the 25 and 16 MHz versions of the 80960CA For a detailed description of any 80960CA functional topic other than parametric performance consult the 80960CA Product Overview (Order No 270669) or the i960 CA Microprocessor User's Manual (Order No 270710) To obtain data sheet updates and errata please call Intel's FaxBACK data-on-demand system (1-800-628-2283 or 916-356-3105) Other information can be obtained from Intel's technical BBS (916-356-3600)
2 0 80960CA OVERVIEW
The 80960CA is the second-generation member of the 80960 family of embedded processors The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware Multiple 128-bit internal buses on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions every clock and peak at execution of three instructions per clock
271327 - 1
Figure 1 80960CA Block Diagram
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SPECIAL ENVIRONMENT 80960CA-25 -16
2 1 The C-Series Core
The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture The C-Series core can sustain execution of two instructions per clock (50 MIPs at 25 MHz) To achieve this level of performance Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core Factors that contribute to the core's performance include
Demultiplexed Burst Bus to exploit most efficient
DRAM access modes
Address Pipelining to reduce memory cost while
maintaining performance
32- 16- and 8-bit modes for I O interfacing ease Full internal wait state generation to reduce system cost
Little and Big Endian support to ease application
development
Parallel instruction decoding allows issuance of
up to three instructions per clock
Unaligned access support for code portability Three-deep request queue to decouple the bus
from the core
Single-clock execution of most instructions Parallel instruction decode allows sustained
simultaneous execution of two single-clock instructions every clock cycle
2 3 Flexible DMA Controller
A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory The DMA provides advanced features such as data chaining byte assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to 45 Mbytes per second at 25 MHz The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CA core
Efficient instruction pipeline minimizes pipeline
break losses
Register and resource scoreboarding allow simultaneous multi-clock instruction execution Branch look-ahead and prediction allows many branches to execute with no pipeline break
Local Register Cache integrated on-chip caches
Call Return context
Two-way set associative 1 Kbyte integrated instruction cache
2 4 Priority interrupt Controller
A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit external interrupt port The interrupt Unit also handles the four internal sources from the DMA controller and a single non-maskable interrupt input The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered Interrupts in the 80960CA are prioritized and signaled within 270 ns of the request If the interrupt is of higher priority than the processor priority the context switch to the interrupt routine typically is complete in another 480 ns The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications
1 Kbyte integrated Data RAM sustains a fourword (128-bit) access every clock cycle
2 2 Pipelined Burst Bus
A 32-bit high performance bus controller interfaces the 80960CA to external memory and peripherals The Bus Control Unit features a maximum transfer rate of 100 Mbytes per second (at 25 MHz) Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance The Bus Controller's main features include
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SPECIAL ENVIRONMENT 80960CA-25 -16
2 5 Instruction Set Summary
Table 1 summarizes the 80960CA instruction set by logical groupings See the i960 User's Manual for a complete description of the instruction set Table 1 80960CA Instruction Set Data Movement Load Store Move Load Address Arithmetic Add Subtract Multiply Divide Remainder Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Branch Unconditional Branch Conditional Branch Compare and Branch Logical And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Bit and Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal
CA Microprocessor
Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark
Call Return Call Call Extended Call System Return Branch and Link
Fault Conditional Fault Synchronize Faults
Processor Management Flush Local Registers Modify Arithmetic Controls Modify Process Controls System Control DMA Control
Atomic Atomic Add Atomic Modify
NOTES Instructions marked by ( ) are 80960CA extensions to the 80960 instruction set
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SPECIAL ENVIRONMENT 80960CA-25 -16
3 0 PACKAGE INFORMATION 3 1 Package Introduction
This section describes the pins pinouts and thermal characteristics for the 80960CA in the 168-pin Ceramic Pin Grid Array (PGA) package For complete package specifications and information see the Packaging Handbook (Order No 240800) I
Table 2 Pin Description Nomenclature Symbol Input only pin Output only pin Pin can be either an input or output Pins ``must be'' connected as described S( ) Synchronous Inputs must meet setup and hold times relative to PCLK2 1 for proper operation All outputs are synchronous to PCLK2 1 S(E) Edge sensitive input S(L) Level sensitive input Asynchronous Inputs may be asynchronous to PCLK2 1 A(E) Edge sensitive input A(L) Level sensitive input While the processor's bus is in the Hold Acknowledge or Bus Backoff state the pin H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid input While the processor's RESET pin is low the pin R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output Description
O IO
3 2 Pin Descriptions
The 80960CA pins are described in this section Table 2 presents the legend for interpreting the pin descriptions in the following tables Pins associated with the 32-bit demultiplexed processor bus are described in Table 3 Pins associated with basic processor configuration and control are described in Table 4 Pins associated with the 80960CA DMA Controller and Interrupt Unit are described in Table 5 All pins float while the processor is in the ONCE mode
A( )
H( )
R( )
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 3 80960CA Pin Description Name A31 2 Type O S H(Z) R(Z) IO S(L) H(Z) R(Z) O S H(Z) R(1)
External Bus Signals
Description ADDRESS BUS carries the physical address' upper 30 bits A31 is the most significant address bit A2 is the least significant During a bus access A31 2 identify all external addresses to word (4-byte) boundaries The byte enable signals indicate the selected byte in each word During burst accesses A3 2 increment to indicate successive data cycles DATA BUS carries 32- 16- or 8-bit data quantities depending on bus width configuration The least significant bit of the data is carried on D0 and the most significant on D31 When the bus is configured for 8-bit data the lower 8 data lines D7 0 are used For 16-bit data bus widths D15 0 are used For 32 bit bus widths the full data bus is used BYTE ENABLES select which of the four bytes addressed by A31 2 are active during an access to a memory region configured for a 32-bit data-bus width BE3 applies to D31 24 BE2 applies to D23 16 BE1 applies to D15 8 BE0 applies to D7 0 32-bit bus BE3 Byte Enable 3 enable D31 24 Byte Enable 2 enable D23 16 BE2 BE1 Byte Enable 1 enable D15 8 BE0 Byte Enable 0 enable D7 0 For accesses to a memory region configured for a 16-bit data-bus width the processor uses the BE3 BE1 and BE0 pins as BHE A1 and BLE respectively 16-bit bus BE3 Byte High Enable (BHE) enable D15 8 BE2 Not used (driven high or low) BE1 Address Bit 1 (A1) Byte Low Enable (BLE) enable D7 0 BE0 For accesses to a memory region configured for an 8-bit data-bus width the processor uses the BE1 and BE0 pins as A1 and A0 respectively 8-bit bus BE3 Not used (driven high or low) BE2 Not used (driven high or low) BE1 Address Bit 1 (A1) BE0 Address Bit 0 (A0) WRITE READ is asserted for read requests and deasserted for write requests The W R signal changes in the same clock cycle as ADS It remains valid for the entire access in non-pipelined regions In pipelined regions W R is not guaranteed to be valid in the last cycle of a read access ADDRESS STROBE indicates a valid address and the start of a new bus access ADS is asserted for the first clock of a bus access
D31 0
BE3 0
WR
O S H(Z) R(0) O S H(Z) R(1)
ADS
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 3 80960CA Pin Description Name READY Type I S(L) H(Z) R(Z)
External Bus Signals (Continued) Description
READY is an input which signals the termination of a data transfer READY is used to indicate that read data on the bus is valid or that a write-data transfer has completed The READY signal works in conjunction with the internally programmed wait-state generator If READY is enabled in a region the pin is sampled after the programmed number of wait-states has expired If the READY pin is deasserted wait states continue to be inserted until READY becomes asserted This is true for the NRAD NRDD NWAD and NWDD wait states The NXDA wait states cannot be extended BURST TERMINATE is an input which breaks up a burst access and causes another address cycle to occur The BTERM signal works in conjunction with the internally programmed wait-state generator If READY and BTERM are enabled in a region the BTERM pin is sampled after the programmed number of wait states has expired When BTERM is asserted a new ADS signal is generated and the access is completed The READY input is ignored when BTERM is asserted BTERM must be externally synchronized to satisfy BTERM setup and hold times WAIT indicates internal wait state generator status WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs WAIT can be used to derive a write-data strobe WAIT can also be thought of as a READY output that the processor provides when it is inserting wait states BURST LAST indicates the last transfer in a bus access BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access If the READY or BTERM input is used to extend wait states the BLAST signal remains asserted until READY or BTERM terminates the access DATA TRANSMIT RECEIVE indicates direction for data transceivers DT R is used in conjunction with DEN to provide control for data transceivers attached to the external bus When DT R is asserted the signal indicates that the processor receives data Conversely when deasserted the processor sends data DT R changes only while DEN is high DATA ENABLE indicates data cycles in a bus request DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle DEN is used in conjunction with DT R to provide control for data transceivers attached to the external bus DEN remains asserted for sequential reads from pipelined memory regions DEN is deasserted when DT R changes BUS LOCK indicates that an atomic read-modify-write operation is in progress LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation LOCK is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation To allow the most flexibility for memory system enforcement of locked accesses the processor acknowledges a bus hold request when LOCK is asserted The processor performs DMA transfers while LOCK is active HOLD REQUEST signals that an external agent requests access to the external bus The processor asserts HOLDA after completing the current bus request HOLD HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents
BTERM
I S(L) H(Z) R(Z)
WAIT
O S H(Z) R(1) O S H(Z) R(0)
BLAST
DT R
O S H(Z) R(0) O S H(Z) R(1)
DEN
LOCK
O S H(Z) R(1)
HOLD
I S(L) H(Z) R(Z)
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 3 80960CA Pin Description Name BOFF Type I S(L) H(Z) R(Z) O S H(1) R(Q)
External Bus Signals (Continued) Description
BUS BACKOFF when asserted suspends the current access and causes the bus pins to float When BOFF is deasserted the ADS signal is asserted on the next clock cycle and the access is resumed HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus When HOLDA is asserted the external address bus data bus and bus control signals are floated HOLD BOFF HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted the state of the HOLDA pin is independent of the RESET pin BUS REQUEST is asserted when the bus controller has a request pending BREQ can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor DATA OR CODE is asserted for a data request and deasserted for instruction requests D C has the same timing as W R
HOLDA
BREQ
O S H(Q) R(0) O S H(Z) R(Z) O S H(Z) R(Z) O S H(Z) R(Z)
DC
DMA
DMA ACCESS indicates whether the bus request was initiated by the DMA controller DMA is asserted for any DMA request DMA is deasserted for all other requests SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode SUP is asserted when the request has supervisor privileges and is deasserted otherwise SUP can be used to isolate supervisor code and data structures from non-supervisor requests
SUP
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 4 80960CA Pin Description Name RESET Type I A(L) H(Z) R(Z)
Processor Control Signals Description
RESET causes the chip to reset When RESET is asserted all external signals return to the reset state When RESET is deasserted initialization begins When the 2-x clock mode is selected RESET must remain asserted for 32 CLKIN cycles before being deasserted to guarantee correct processor initialization When the 1-x clock mode is selected RESET must remain asserted for 10 000 CLKIN cycles before being deasserted to guarantee correct processor initialization The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin The processor's Hold Acknowledge bus state functions while the chip is reset If the processor's bus is in the Hold Acknowledge state when RESET is asserted the processor will internally reset but maintains the Hold Acknowledge state on external pins until the Hold request is removed If a Hold request is made while the processor is in the reset state the processor bus will grant HOLDA and enter the Hold Acknowledge state FAIL indicates failure of the processor's self-test performed at initialization When RESET is deasserted and the processor begins initialization the FAIL pin is asserted An internal self-test is performed as part of the initialization process If this self-test passes the FAIL pin is deasserted otherwise it remains asserted The FAIL pin is reasserted while the processor performs an external bus self-confidence test If this self-test passes the processor deasserts the FAIL pin and branches to the user's initialization routine otherwise the FAIL pin remains asserted Internal self-test and the use of the FAIL pin can be disabled with the STEST pin SELF TEST causes the processor's internal self-test feature to be enabled or disabled at initialization STEST is read on the rising edge of RESET When asserted the processor's internal self-test and external bus confidence tests are performed during processor initialization When deasserted only the bus confidence tests are performed during initialization ON CIRCUIT EMULATION when asserted causes all outputs to be floated ONCE is continuously sampled while RESET is low and is latched on the rising edge of RESET To place the processor in the ONCE state (1) assert RESET and ONCE (order does not matter) (2) wait for at least 16 CLKIN periods in 2-x mode or 10 000 CLKIN periods in 1-x mode after VCC and CLKIN are within operating specifications (3) deassert RESET (4) wait at least 32 CLKIN periods (The processor will now be latched in the ONCE state as long as RESET is high ) To exit the ONCE state bring VCC and CLKIN to operating conditions then assert RESET and bring ONCE high prior to deasserting RESET CLKIN must operate within the specified operating conditions of the processor until Step 4 above has been completed CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current ONCE can be used by emulator products or for board testers to effectively make an installed processor transparent in the board
FAIL
O S H(Q) R(0)
STEST
I S(L) H(Z) R(Z) I A(L) H(Z) R(Z)
ONCE
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 4 80960CA Pin Description Name CLKIN Type I A(E) H(Z) R(Z) I A(L) H(Z) R(Z)
Processor Control Signals (Continued) Description
CLOCK INPUT is an input for the external clock needed to run the processor The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2 1 CLOCK MODE selects the division factor applied to the external clock input (CLKIN) When CLKMODE is high CLKIN is divided by one to create PCLK2 1 and the processor's internal clock When CLKMODE is low CLKIN is divided by two to create PCLK2 1 and the processor's internal clock CLKMODE should be tied high or low in a system as the clock mode is not latched by the processor If left unconnected the processor will internally pull the CLKMODE pin low enabling the 2-x clock mode PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor inputs and outputs All input and output timings are specified in relation to PCLK2 and PCLK1 PCLK2 and PCLK1 are identical signals Two output pins are provided to allow flexibility in the system's allocation of capacitive loading on the clock PCLK2 1 may also be connected at the processor to form a single clock signal GROUND connections must be connected externally to a VSS board plane POWER connections must be connected externally to a VCC board pane VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments Otherwise VCCPLL should be connected to VCC This pin is implemented starting with the D-stepping See Table 13 for die stepping information NO CONNECT pins must not be connected in a system
CLKMODE
PCLK2 1
O S H(Q) R(Q)
VSS VCC VCCPLL
NC
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 5 80960CA Pin Description Name DREQ3 0 Type I A(L) H(Z) R(Z) O S H(1) R(1) IO A(L) H(Z Q) R(Z)
DMA and Interrupt Unit Control Signals Description
DMA REQUEST causes a DMA transfer to be requested Each of the four signals requests a transfer on a single channel DREQ0 requests channel 0 DREQ1 requests channel 1 etc When two or more channels are requested simultaneously the channel with the highest priority is serviced first The channel priority mode is programmable DMA ACKNOWLEDGE indicates that a DMA transfer is being executed Each of the four signals acknowledges a transfer for a single channel DACK0 acknowledges channel 0 DACK1 acknowledges channel 1 etc DACK3 0 are asserted when the requesting device of a DMA is accessed END OF PROCESS TERMINAL COUNT can be programmed as either an input (EOP3 0) or as an output (TC3 0) but not both Each pin is individually programmable When programmed as an input EOPx causes the termination of a current DMA transfer for the channel corresponding to the EOPx pin EOP0 corresponds to channel 0 EOP1 corresponds to channel 1 etc When a channel is configured for source and destination chaining the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred EOP3 0 are asynchronous inputs When programmed as an output the channel's TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer If the last bus request is executed as multiple bus accesses TCx will stay asserted for the entire bus request EXTERNAL INTERRUPT PINS cause interrupts to be requested These pins can be configured in three modes Dedicated Mode each pin is a dedicated external interrupt source Dedicated inputs can be individually programmed to be level (low) or edge (falling) activated Expanded Mode the eight pins act together as an 8-bit vectored interrupt source The interrupt pins in this mode are level activated Since the interrupt pins are active low the vector number requested is the one's complement of the positive logic value place on the port This eliminates glue logic to interface to combinational priority encoders which output negative logic Mixed Mode XINT7 5 are dedicated sources and XINT4 0 act as the five most significant bits of an expanded mode vector The least significant bits are set to 010 internally NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur NMI is the highest priority interrupt recognized NMI is an edge (falling) activated source
DACK3 0
EOP TC3 0
XINT7 0
I A(E L) H(Z) R(Z)
NMI
I A(E) H(Z) R(Z)
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SPECIAL ENVIRONMENT 80960CA-25 -16
the component (i e pins facing down) Figure 3 shows the complete 80960CA PGA pinout as viewed from the pin-side of the package (i e pins facing up) See Section 4 0 ELECTRICAL SPECIFICATIONS for specifications and recommended connections
3 3 80960CA Mechanical Data
3 3 1 80960CA PGA Pinout Tables 6 and 7 list the 80960CA pin names with package location Figure 2 depicts the complete 80960CA PGA pinout as viewed from the top side of
Table 6 80960CA PGA Pinout Address Bus Signal A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin S15 Q13 R14 Q14 S16 R15 S17 Q15 R16 R17 Q16 P15 P16 Q17 P17 N16 N17 M17 L16 L17 K17 J17 H17 G17 G16 F17 E17 E16 D17 D16 Data Bus Signal D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pin R3 Q5 S2 Q4 R2 Q3 S1 R1 Q2 P3 Q1 P2 P1 N2 N1 M1 L1 L2 K1 J1 H1 H2 G1 F1 E1 F2 D1 E2 C1 D2 C2 E3 BOFF B1 DC DMA SUP S13 R12 Q12 HOLD HOLDA BREQ R5 S4 R13 LOCK S14 DT R DEN S11 S9 WAIT BLAST S12 S8 READY BTERM S3 R4 ADS R6 WR S10 Bus Control Signal BE3 BE2 BE1 BE0 Pin S5 S6 S7 R9
In Signal Order Processor Control Signal RESET FAIL STEST ONCE CLKIN CLKMODE PLCK1 PLCK2 VSS Pin A16 A2 B2 DACK3 C3 C13 C14 B14 B13 EOP TC3 EOP TC2 EOP TC1 EOP TC0 XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 NMI A14 A13 A12 A11 C17 C16 B17 C15 B16 A17 A15 B15 D15 DACK2 DACK1 DACK0 A10 A9 A8 B8 IO Signal DREQ3 DREQ2 DREQ1 DREQ0 Pin A7 B6 A6 B5
Location
C7 C8 C9 C10 C11 C12 F15 G3 G15 H3 H15 J3 J15 K3 K15 L3 L15 M3 M15 Q7 Q8 Q9 Q10 Q11 VCC
Location
B7 C6 G2 K2 N3 R8 B9 B11 B12 E15 F3 F16 H16 J2 J16 K16 M2 M16 N15 Q6 R7 R10 R11 B10
VCCPLL
No Connect
Location
A1 A3 A4 A5 B3 B4 C4 C5 D3
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 7 80960CA PGA Pinout Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 Signal NC FAIL NC NC NC DREQ1 DREQ3 DACK1 DACK2 DACK3 EOP TC0 EOP TC1 EOP TC2 EOP TC3 XINT1 RESET XINT2 BOFF STEST NC NC DREQ0 DREQ2 VCC DACK0 VCC VCCPLL VCC VCC PCLK2 PCLK1 XINT0 XINT3 XINT5 F1 F2 F3 F15 F16 F17 D8 D6 VCC VSS VCC A6 E1 E2 E3 E15 E16 E17 D7 D4 D0 VCC A4 A5 L1 L2 L3 L15 L16 L17 D15 D14 VSS VSS A13 A12 Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 D17 Signal D3 D1 ONCE NC NC VCC VSS VSS VSS VSS VSS VSS CLKIN CLKMODE XINT4 XINT6 XINT7 D5 D2 NC NMI A2 A3 K1 K2 K3 K15 K16 K17 D13 VCC VSS VSS VCC A11 J1 J2 J3 J15 J16 J17 D12 VCC VSS VSS VCC A10 H1 H2 H3 H15 H16 H17 D11 D10 VSS VSS VCC A9 Pin G1 G2 G3 G15 G16 G17 D9 VCC VSS VSS A7 A8
In Pin Order Pin M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Signal D16 VCC VSS VSS VCC A14 D17 D18 VCC VCC A16 A15 D19 D20 D22 A20 A19 A17 D21 D23 D26 Q28 D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 A21 A18 S1 S2 S3 S4 S5 56 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 D25 D29 READY HOLDA BE3 BE2 BE1 BLAST DEN WR DT R WAIT DC LOCK A31 A27 A25 Pin R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 Signal D24 D27 D31 BTERM HOLD ADS VCC VCC BE0 VCC VCC DMA BREQ A29 A26 A23 A22
Signal
16
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 2
Figure 2 80960CA PGA Pinout
View from Top (Pins Facing Down)
17
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 3
Figure 3 80960CA PGA Pinout
View from Bottom (Pins Facing Up)
18
SPECIAL ENVIRONMENT 80960CA-25 -16
TA e TC b P iCA Table 8 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK) Note that TA is greatly improved by attaching fins or a heatsink to the package P (maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4 4 DC Specifications and VCC of 5V
3 4 Package Thermal Specifications
The 80960CA is specified for operation when TC (case temperature) is within the range of b 40 C - a 110 C TC may be measured in any environment to determine whether the 80960CA is within specified operating range Case temperature should be measured at the center of the top surface opposite the pins Refer to Figure 4 TA (ambient temperature) can be calculated from iCA (thermal resistance from case to ambient) using the following equation
271327 - 4
Figure 4 Measuring 80960CA PGA Case Temperature Table 8 Maximum TA at Various Airflows in C Airflow-ft min (m sec) fPCLK (MHz) TA with Heatsink TA without Heatsink 33 25 16 33 25 16 0 (0) 51 61 74 36 49 66 200 (1 01) 66 73 82 47 58 72 400 (2 03) 79 83 89 59 67 78 600 (3 04) 81 85 90 66 73 82 800 (4 06) 85 88 92 73 78 86 1000 (5 07) 87 89 93 75 80 87
NOTES 0 285 high undirectional heatsink (Al alloy 6061 50 mil fin width 150 mil center-to-center fin spacing)
19
SPECIAL ENVIRONMENT 80960CA-25 -16
Table 9 80960CA PGA Package Thermal Characteristics Thermal Resistance Airflow Parameter i Junction-to-Case (Case measured as shown in Figure 4) i Case-to-Ambient (No Heatsink) i Case-to-Ambient (With Heatsink) 0 (0) 15 200 (1 01) 15 400 (2 03) 15 C Watt ft min (m sec) 600 (3 07) 15 800 (4 06) 15 1000 (5 07) 15
17 13
14 9
11 55
9 5
71 39
66 34
NOTES 1 This table applies to 80960CA PGA plugged into socket or soldered directly to board 2 iJA e iJC a iCA 0 285 high unidirectional heatsink (Al alloy 6061 50 mil fin width 150 mil center-to-center fin spacing)
20
SPECIAL ENVIRONMENT 80960CA-25 -16
3 5 Stepping Register Information
Upon reset register g0 contains die stepping information Figure 5 shows how g0 is configured The most significant byte contains an ASCII 0 The upper middle byte contains an ASCII C The lower middle byte contains an ASCII A The least significant byte contains the stepping number in ASCII g0 retains this information until it is overwritten by the user program
3 6 Suggested Sources for 80960CA Accessories
The following is a list of suggested sources for 80960CA accessories This is not an endorsement of any kind nor is it a warranty of the performance of any of the listed products and or companies Sockets 1 3M Textool Test and Interconnection Products Department P O Box 2963 Austin TX 78769-2963 2 Augat Inc Interconnection Products Group 33 Perry Avenue P O Box 779 Attleboro MA 02703 (508) 699-7646 3 Concept Manufacturing Inc (Decoupling Sockets) 41484 Christy Street Fremont CA 94538 (415) 651-3804 Heatsinks Fins
ASCII DECIMAL
00 0 MSB
43 C
41 A
Stepping Number Stepping Number LSB
Figure 5 Register g0 Table 10 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number Table 10 Die Stepping Cross Reference g0 Least Significant Byte 01 02 03 04 Die Stepping B C-1 C-2 C-3 D
1 Thermalloy Inc 2021 West Valley View Lane Dallas TX 75234-8993 (214) 243-4321 FAX (214) 241-4656 2 E G G Division 60 Audubon Road Wakefield MA 01880 (617) 245-5900
21
SPECIAL ENVIRONMENT 80960CA-25 -16
4 0 ELECTRICAL SPECIFICATIONS 4 1 Absolute Maximum Ratings
Storage Temperature Case Temperature Under Bias Supply Voltage with Respect to VSS Voltage on Other Pins with Respect to VSS
b 65 C to a 150 C b 40 C to a 110 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
4 2 Operating Conditions
Table 11 Operating Conditons (80960CA-25 -16) Symbol VCC fCLK2x fCLK1x TC Supply Voltage Input Clock Frequency (2-x Mode) Input Clock Frequency (1-x Mode) Case Temperature Under Bias Parameter 80960CA-25 80960CA-16 80960CA-25 80960CA-16 80960CA-25 80960CA-16 PGA package 80960CA-25 -16 Min 4 50 4 50 0 0 8 8
b 40
Max 5 50 5 50 50 32 25 16
a 110
Units V V MHz MHz MHz MHz C
Notes
(Note 1)
NOTES 1 When in the 1-x input clock mode CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation However in the 1-x mode CLKIN may still be stopped when the processor either is in a reset condition or is reset If CLKIN is stopped the specified RESET low time must be provided once CLKIN restarts and has stabilized 2 Case temperatures are ``instant on''
4 3 Recommended Connections
Power and ground connections must be made to multiple VCC and VSS (GND) pins Every 80960CAbased circuit board should include power (VCC) and ground (VSS) planes for power distribution Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Pins identified as ``NC'' must not be connected in the system Liberal decoupling capacitance should be placed near the 80960CA The processor can cause transient power surges when its numerous output buffers transition particularly when connected to large capacitive loads
Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible Capacitors specifically designed for PGA packages will offer the lowest possible inductance For reliable operation always connect unused inputs to an appropriate signal level In particular any unused interrupt (XINT NMI) or DMA (DREQ) input should be connected to VCC through a pull-up resistor as should BTERM if not used Pull-up resistors should be in the in the range of 20 KX for each pin tied high If READY or HOLD are not used the unused input should be connected to ground N C pins must always remain unconnected Refer to the i960 CA Microprocessor User's Manual (Order Number 270710) for more information
22
SPECIAL ENVIRONMENT 80960CA-25 -16
4 4 DC Specifications
Table 12 DC Characteristics (80960CA-25 -16 under the conditions described in Section 4 2 Operating Conditions ) Symbol VIL VIH VOL VOH VILR VIHR ILI1 Parameter Input Low Voltage for all pins except RESET Input High Voltage for all pins except RESET Output Low Voltage Output High Voltage IOH e b 1 mA IOH e b 200 mA 24 VCC b 0 5
b0 3
Min
b0 3
Max
a0 8
Units V V V V V
Notes
20
VCC a 0 3 0 45
IOL e 5 mA
Input Low Voltage for RESET Input High Voltage for RESET Input Leakage Current for each pin except BTERM ONCE DREQ3 0 STEST EOP3 0 TC3 0 NMI XINT7 0 BOFF READY HOLD CLKMODE Input Leakage Current for BTERM ONCE DREQ3 0 STEST EOP3 0 TC3 0 NMI XINT7 0 BOFF Input Leakage Current for READY HOLD CLKMODE Output Leakage Current Supply Current (80960CA-25) ICC Max ICC Typ
15 VCC a 0 3
V V
35
g15
mA
0 s VIN s VCC(1)
ILI2
0 0
b 325
mA mA mA mA mA mA mA mA
VIN e 0 45V(2) VIN e 2 4V(3 7) 0 45 s VOUT s VCC (Note 4) (Note 5) (Note 4) (Note 5)
ILI3 ILO ICC
500
g15
750 600 550 400 100
ICC
Supply Current (80960CA-16) ICC Max ICC Typ
IONCE CIN
ONCE-mode Supply Current Input Capacitance for CLKIN RESET ONCE READY HOLD DREQ3 0 BOFF XINT7 0 NMI BTERM CLKMODE Output Capacitance of each output pin I O Pin Capacitance
0
12 12 12
pF pF pF
FC e 1 MHz FC e 1 MHz(6) FC e 1 MHz
COUT CI O
NOTES 1 No pullup or pulldown 2 These pins have internal pullup resistors 3 These pins have internal pulldown resistors 4 Measured at worst case frequency VCC and temperature with device operating and outputs loaded to the test conditions described in Section 4 5 1 AC Test Conditions 5 ICC Typical is not tested 6 Output Capacitance is the capacitive load of a floating output 7 CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted
23
SPECIAL ENVIRONMENT 80960CA-25 -16
4 5 AC Specifications
Table 13 80960CA AC Characteristics (25 MHz) (80960CA-25 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions )
Symbol Input Clock (1 9) TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOH TOV CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to PCLK2 1 Delay PCLK2 1 Period PCLK2 1 High Time PCLK2 1 Low Time PCLK2 1 Rise Time PCLK2 1 Fall Time Output Valid Delay Output Hold TOH1 TOV1 TOH2 TOV2 TOH3 TOV3 TOH4 TOV4 TOH5 TOV5 TOH6 TOV6 TOH7 TOV7 TOH8 TOV8 TOH9 TOV9 TOH10 TOV10 TOH11 TOV11 TOH12 TOV12 TOH13 TOV13 TOH14 TOV14 Output Float for all ouputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 8 8 8 8 0 0
b2
Parameter
Min 0 40 20
Max 50 125 %
g0 1%
Units MHz ns ns D ns ns ns ns ns ns ns ns ns ns
Notes
(11) (12) (11) (11)
62 5 % 62 5 % 6 6 2 25 TC 2TC
Output Clocks (1 8) 2 (3 12) (3) (12) (3) (12) (12) (3) (3) (6 10) A31 2 BE3 0 ADS WR D C SUP DMA BLAST WAIT DEN HOLDA BREQ LOCK DACK3 0 D31 0 DT R FAIL EOP3 0 TC3 0 3 3 6 3 4 5 3 4 4 4 3 T 2a3 2 3 3 16 18 20 20 18 18 18 18 18 20 18 T 2 a 16 16 20 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(T 2) b 3 (T 2) b 3 1 1
T2 T2 4 4
ns ns ns ns
Synchronous Outputs (8)
(6 10) (6)
TOF TIS
Synchronous Inputs (1 9 10) D31 0 BOFF BTERM READY HOLD D31 0 BOFF BTERM READY HOLD 5 19 9 9 5 7 2 5 ns ns ns ns ns ns ns ns
TIH
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SPECIAL ENVIRONMENT 80960CA-25 -16
Table 13 80960CA AC Characteristics (25 MHz) (Continued) (80960CA-25 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions )
Symbol TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 Parameter A31 2 Valid to ADS Rising BE3 0 W R SUP D C DMA DACK3 0 Valid to ADS Rising A31 2 Valid to DEN Falling BE3 0 W R SUP INST DMA DACK3 0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT R Hold after DEN High DT R Valid to DEN Falling RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3 0 Input Setup DREQ3 0 Input Hold XINT7 0 NMI Input Setup XINT7 0 NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) T 2b7 T 2b4 8 7 14 9 10 10 3 T 4a1 N Tb4 N Tg4 (N a 1) T b 8 (N a 1) T a 6 % Min Tb4 Tb6 Tb4 Tb6
g4
Max Ta4 Ta6 Ta4 Ta6 N Ta4
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
Relative Output Timings (1 2 3 8)
(4) (4) (5) (6)
Relative Input Timings (1 2 3) (13) (13) (7) (7) (15) (15) (14) (14)
NOTES 1 See Section 4 5 2 AC Timing Waveforms for waveforms and definitions 2 See Figure 16 for capacitive derating information for output delays and hold times 3 See Figure 17 for capacitive derating information for rise and fall times 4 Where N is the number of NRAD NRDD NWAD or NWDD wait states that are programmed in the Bus Controller Region Table WAIT never goes active when there are no wait states in an access 5 N e Number of wait states inserted with READY 6 Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity 7 Since asynchronous inputs are synchronized internally by the 80960CA they have no required setup or hold times to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising edges to be seen by the processor 8 These specifications are guaranteed by the processor 9 These specifications must be met by the system for proper operation of the processor 10 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 Derating Curves to adjust the timing for PCLK2 1 loading 11 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When the processor is in reset the input clock may stop even in 1-x mode 12 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than g0 1% between adjacent cycles 13 In 2-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the falling edge of the CLKIN (See Figure 21) 14 In 1-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the rising edge of the CLKIN (See Figure 22 ) 15 The interrupt pins are synchronized internally by the 80960CA They have no required setup or hold times for proper operation These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2 1 rising edges when asserting them asynchronously To guarantee recognition at a particular clock edge the setup and hold times shown must be met for two consecutive PCLK2 1 rising edges
25
SPECIAL ENVIRONMENT 80960CA-25 -16
Table 14 80960CA AC Characteristics (16 MHz) (80960CA-16 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions )
Symbol Input Clock (1 9) TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOH TOV CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to PCLK2 1 Delay PCLK2 1 Period PCLK2 1 High Time PCLK2 1 Low Time PCLK2 1 Rise Time PCLK2 1 Fall Time Output Valid Delay Output Hold TOH1 TOV1 TOH2 TOV2 TOH3 TOV3 TOH4 TOV4 TOH5 TOV5 TOH6 TOV6 TOH7 TOV7 TOH8 TOV8 TOH9 TOV9 TOH10 TOV10 TOH11 TOV11 TOH12 TOV12 TOH13 TOV13 TOH14 TOV14 Output Float for All Ouputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 10 10 10 10 0 0
b2
Parameter
Min 0 62 5 31 25
Max 32 125 %
g0 1%
Units MHz ns ns D ns ns ns ns ns ns ns ns ns ns
Notes
(11) (12) (11) (11)
62 5 % 62 5 % 6 6 2 25 TC 2TC
Output Clocks (1 8) 2 (3 12) (3) (12) (3) (12) (12) (3) (3) (6 10) A31 2 BE3 0 ADS WR D C SUP DMA BLAST WAIT DEN HOLDA BREQ LOCK DACK3 0 D31 0 DT R FAIL EOP3 0 TC3 0 3 3 6 3 4 5 3 4 4 4 3 T 2a3 2 3 3 18 20 22 22 20 20 20 20 20 22 20 T 2 a 18 18 22 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(T 2) b 4 (T 2) b 4 1 1
T2 T2 4 4
ns ns ns ns
Synchronous Outputs (8)
(6 10) (6)
TOF TIS
Synchronous Inputs (1 9 10) D31 0 BOFF BTERM READY HOLD D31 0 BOFF BTERM READY HOLD 5 21 9 9 5 7 2 5 ns ns ns ns ns ns ns ns
TIH
26
SPECIAL ENVIRONMENT 80960CA-25 -16
Table 14 80960CA AC Characteristics (16 MHz) (Continued) (80960CA-16 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions )
Symbol TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 Parameter A31 2 Valid to ADS Rising BE3 0 W R SUP D C DMA DACK3 0 Valid to ADS Rising A31 2 Valid to DEN Falling BE3 0 W R SUP INST DMA DACK3 0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT R Hold after DEN High DT R Valid to DEN Falling RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3 0 Input Setup DREQ3 0 Input Hold XINT7 0 NMI Input Setup XINT7 0 NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) T 2b7 T 2b4 10 9 16 11 10 10 3 T 4a1 N Tb4 N Tg4 (N a 1) T b 8 (N a 1) T a 4 % Min Tb4 Tb6 Tb6 Tb6
g4
Max Ta4 Ta6 Ta6 Ta6 N Ta4
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
Relative Output Timings (1 2 3 8)
(4) (4) (5) (6)
Relative Input Timings (1 2 3) (13) (13) (7) (7) (15) (15) (14) (14)
NOTES 1 See Section 4 5 2 AC Timing Waveforms for waveforms and definitions 2 See Figure 16 for capacitive derating information for output delays and hold times 3 See Figure 17 for capacitive derating information for rise and fall times 4 Where N is the number of NRAD NRDD NWAD or NWDD wait states that are programmed in the Bus Controller Region Table WAIT never goes active when there are no wait states in an access 5 N e Number of wait states inserted with READY 6 Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity 7 Since asynchronous inputs are synchronized internally by the 80960CA they have no required setup or hold times to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising edges to be seen by the processor 8 These specifications are guaranteed by the processor 9 These specifications must be met by the system for proper operation of the processor 10 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 Derating Curves to adjust the timing for PCLK2 1 loading 11 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When the processor is in reset the input clock may stop even in 1-x mode 12 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than g0 1% between adjacent cycles 13 In 2-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the falling edge of the CLKIN (See Figure 21) 14 In 1-x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the rising edge of the CLKIN (See Figure 22 ) 15 The interrupt pins are synchronized internally by the 80960CA They have no required setup or hold times for proper operation These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2 1 rising edges when asserting them asynchronously To guarantee recognition at a particular clock edge the setup and hold times shown must be met for two consecutive PCLK2 1 rising edges
27
SPECIAL ENVIRONMENT 80960CA-25 -16
4 5 1 AC Test Conditions The AC Specifications in Section 4 5 are tested with the 50 pF load shown in Figure 6 Figure 15 shows how timings vary with load capacitance Specifications are measured at the 1 5V crossing point unless otherwise indicated Input waveforms are assumed to have a rise and fall time of s 2 ns from 0 8V to 2 0V See Section 4 5 2 AC Timing Waveforms for AC spec definitions test points and illustrations 4 5 2 AC Timing Waveforms
271327 - 6
CL e 50 pF for all signals
Figure 6 AC Test Load
271327 - 7
Figure 7 Input and Output Clock Waveforms
271327 - 8
Figure 8 CLKIN Waveform
28
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 9
Figure 9 Output Delay and Float Waveform
271327 - 10
Figure 10 Input Setup and Hold Waveform TOV TOH OUTPUT DELAY The maximum output delay is referred to as the Output Valid Delay (TOV) The minimum output delay is referred to as the Output Hold (TOH) TOF TIS TIH OUTPUT FLOAT DELAY The output float condition occurs when the maximum output current becomes less than ILO in magnitude INPUT SETUP AND HOLD The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation
29
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 11
Figure 11 NMI XINT7 0 Input Setup and Hold Waveform
271327 - 12
Figure 12 Hold Acknowledge Timings TOV TOH OUTPUT DELAY The maximum output delay is referred to as the Output Valid Delay (TOV) The minimum output delay is referred to as the Output Hold (TOH) TOF OUTPUT FLOAT DELAY The output float condition occurs when the maximum output current becomes less than ILO in magnitude TIS TIH INPUT SETUP AND HOLD The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation
30
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 13
Figure 13 Bus Backoff BOFF Timings
31
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 14
Figure 14 Relative Timings Waveforms 4 5 3 Derating Curves
271327 - 15
NOTE PCLK Load e 50 pF
Figure 15 Output Delay or Hold vs Load Capacitance
32
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 16
a) All outputs except LOCK DMA SUP HOLDA BREQ DACK3 0 EOP3 0 TC3 0 FAIL
b) LOCK DMA SUP EOP3 0 TC3 0 FAIL
HOLDA
BREQ
DACK3 0
Figure 16 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC
271327 - 17
ICC -ICC under test conditions
Figure 17 ICC vs Frequency and Temperature
33
SPECIAL ENVIRONMENT 80960CA-25 -16
Table 16 lists the condition of each processor output pin while HOLDA is asserted (low) Table 16 Hold Acknowledge and Backoff Conditions Pins A31 2 D31 0 BE3 0 WR ADS WAIT BLAST DT R DEN LOCK BREQ DC DMA SUP FAIL DACK3 0 EOP3 0 TC3 0 State During HOLDA Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Driven (High or low) Floating Floating Floating Driven high (Inactive) Driven high (Inactive) Driven (If output)
5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE
Table 15 lists the condition of each processor output pin while RESET is asserted (low) Table 15 Reset Conditions Pins A31 2 D31 0 BE3 0 WR ADS WAIT BLAST DT R DEN LOCK BREQ DC DMA SUP FAIL DACK3 0 EOP3 0 TC3 0 State During Reset (HOLDA Inactive)1 Floating Floating Driven high (Inactive) Driven low (Read) Driven high (Inactive) Driven high (Inactive) Driven low (Active) Driven low (Receive) Driven high (Inactive) Driven high (inactive) Driven low (Inactive) Floating Floating Floating Driven low (Active) Driven high (Inactive) Floating (Set to input mode)
NOTES 1 With regard to bus output pin state only the Hold Acknowledge state takes precedence over the reset state Although asserting the RESET pin will internally reset the processor the processor's bus output pins will not enter the reset state if it has granted Hold Acknowledge to a previous HOLD request (HOLDA is active) Furthermore the processor will grant new HOLD requests and enter the Hold Acknowledge state even while in reset For example if HOLDA is inactive and the processor is in the reset state then HOLD is asserted the processsor's bus pins enter the Hold Acknowledge state and HOLDA is granted The processor will not be able to perform memory accesses until the HOLD request is removed even if the RESET pin is brought high This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus
34
SPECIAL ENVIRONMENT 80960CA-25 -16
6 0 BUS WAVEFORMS
271327 - 18
Figure 18 Cold Reset Waveform
35
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 19
Figure 19 Warm Reset Waveform
36
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 20
Figure 20 Entering the ONCE State
37
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 21
NOTE Case 1 and Case 2 show two possible polarities of PCLK2 1
Figure 21 Clock Synchronization in the 2-x Clock Mode
271327 - 22
NOTE In 1x clock mode the RESET pin is actually sampled on the falling edge of 2xCLK 2xCLK is an internal signal generated by the PLL and is not available on an external pin Therefore RESET is specified relative to the rising edge of CLKIN The RESET pin is sampled when PCLK is high
Figure 22 Clock Synchronization in the 1-x Clock Mode
38
SPECIAL ENVIRONMENT 80960CA-25 -16
271327 - 23
Figure 23 Non-Burst Non-Pipelined Requests Without Wait States
39
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Figure 24 Non-Burst Non-Pipelined Read Request With Wait States
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Figure 25 Non-Burst Non-Pipelined Write Request With Wait States
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Figure 26 Burst Non-Pipelined Read Request Without Wait States 32-Bit Bus
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Figure 27 Burst Non-Pipelined Read Request With Wait States 32-Bit Bus
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Figure 28 Burst Non-Pipelined Write Request Without Wait States 32-Bit Bus
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Figure 29 Burst Non-Pipelined Write Request With Wait States 32-Bit Bus
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Figure 30 Burst Non-Pipelined Read Request With Wait States 16-Bit Bus
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Figure 31 Burst Non-Pipelined Read Request With Wait States 8-Bit Bus
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Figure 32 Non-Burst Pipelined Read Request Without Wait States 32-Bit Bus
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Figure 33 Non-Burst Pipelined Read Request With Wait States 32-Bit Bus
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Figure 34 Burst Pipelined Read Request Without Wait States 32-Bit Bus
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Figure 35 Burst Pipelined Read Request With Wait States 32-Bit Bus
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Figure 36 Burst Pipelined Read Request With Wait States 16-Bit Bus
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Figure 37 Burst Pipelined Read Request With Wait States 8-Bit Bus
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Figure 38 Using External READY
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NOTE READY adds memory access time to data transfers whether or not the bus access is a burst access BTERM interrupts a bus access whether or not the bus access has more data transfers pending Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access
Figure 39 Terminating a Burst with BTERM
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NOTE READY BTERM must be enabled NRAD NRDD NWAD NWDD e 0
Figure 40 BOFF Functional Timing
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Figure 41 HOLD Functional Timing
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NOTES 1 Case 1 DREQ must deassert before DACK deasserts Applications are Fly-By and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores 2 Case 2 DREQ must be deasserted by the second clock (rising edge) after DACK is driven high Applications are non Fly-By transfers and adjacent load-stores or store-loads 3 DACKx is asserted for the duration of a DMA bus request The request may consist of multiple bus accesses (defined by ADS and BLAST Refer to i960 CA Microprocessor User's Manual for ``access'' ``request'' definitions
Figure 42 DREQ and DACK Functional Timing
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NOTE EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests EOP is NOT edge triggered EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles
Figure 43 EOP Functional Timing
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NOTES Terminal Count becomes active during the last bus request of a buffer If the last LOAD STORE bus request is executed as multiple bus accesses the TC will be active for the entire bus request Refer to the i960 CA Microprocessor User's Manual for further information
Figure 44 Terminal Count Functional Timing
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Figure 45 FAIL Functional Timing
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Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
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Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
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Figure 48 Idle Bus Operation
7 0 REVISION HISTORY
New
62
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